The present invention relates to a synchronous semiconductor devices and a synchronous semiconductor device exhibiting an operation synchronous with an externally inputted lock signal.
In recent years, the requirement for improvement in semiconductor memory devices exhibiting high speed performances have been on the increase. In order to realize the semiconductor memory device exhibiting the required high speed performances, there was proposed a synchronous semiconductor memory device operable in synchronizing with the externally inputted lock signal. The conventional dynamic random access memory is of the asynchronous type. Recently, however, the synchronous dynamic random access memory was proposed which is operable in synchronizing with the externally inputted lock signal.
FIG. 1 is a block diagram illustrative of the conventional synchronous dynamic random access memory.
A clock generator circuit 101 is provided for generating a clock signal. A command decoder 102 is also provided which is connected to the clock generator circuit 101 for receiving the clock signal so that the command decoder 102 receives controls signals at the rise-timing of the clock signals. The control signals to be inputted into the command data decoder 102 comprise a chip select bar (CS), a row address strobe bar (RAS), a column address strobe bar (CAS), and a write enable bar (WE). The command decoder 102 decodes the control signals to generate a "command" based upon combination of voltage levels of the control signals. There are also provided a mode resistor 103, a control circuit 106, a row address buffer circuit 104, a column address buffer circuit 105, a row decoder circuit 108, a column decoder circuit 111, a sense amplifier 110, a memory cell array 107, a data control circuit 112, a latch circuit 113, and an input/output buffer 109. The synchronous dynamic random access memory is operated in synchronizing with the clock signal 93 generated by the clock signal generator 101.
The following descriptions are concerned with how to write data into memory cells. An active command is inputted so that an externally inputted address signal is latched as a row address by the row address buffer circuit 104 for subsequent decoding the same by the row decoder circuit 108 to decide the row address thereby to select a word line of the memory cell array 107. Subsequently, a write command is inputted so that the externally inputted address signal is latched as a column address by the column address buer circuit 105 to decide the row address thereby to select Y-switch not illustrated, whereby the externally inputted write data are written into the memory cells. Finally, a precharge command is inputted to make non-selected state the word line selected in accordance with the active command.
The operation of reading out data will subsequently be described. At the same time when data are written, the row address is decided in accordance with the active command before a read command is inputted.
Processings of the internal command signals and the internal control signals will be described with reference to FIGS. 2 and 3. FIG. 2 is a block diagram illustrative of a row address control signal generator circuit in the conventional synchronous dynamic random access memory of FIG. 1. FIG. 3 is a diagram illustrative of waveforms of internal command signals and internal control signals in the conventional synchronous dynamic random access memory.
A command decoder 81 of FIG. 2 corresponds to the command decoder 102 of FIG. 1. A row address control signal generator circuit 82 of FIG. 2 corresponds to a row address control signal generator circuit accommodated in the control circuit 106. The command decoder 81 generates internal command signals 71 and 72. The row address control signal generator circuit 82 is connected to the command decoder 81 for receiving the internal command signals 71 and 72 from the command decoder 81. The row address control signal generator circuit 82 comprises a flip-flop circuit and a series connection of first and second invertors 86 and 87. The flip-flop circuit comprises first and second NOR gates 84 and 85. The first NOR gate 84 has two input terminals connected to the command decoder 81 and an output terminal of the second NOR gate 85 for receiving the internal command signal 71 and an output signal from the second NOR gate 85. The first NOR gate 84 also has an output terminal connected to an input terminal of the invertor 86 and also connected to one of the two input terminals of the second NOR gate 85 for transmitting an output signal to the invertor 86 and the second NOR gate 85. The second NOR gate 85 has two input terminals connected to the command decoder 81 and the output terminal of the first NOR gate 84 for receiving the internal command signal 72 and the output signal from the first NOR gate 84. The second NOR gate 85 also has an output terminal connected to one of the two input terminals of the first NOR gate 84 for transmitting an output signal to the first NOR gate 84. The first invertor 86 receives the output signal from the first NOR gate 84. The second invertor 87 receives an output signal from the first invertor 86 and outputs a row address control signal 73.
Operations of the row address control signal generator circuit in the conventional synchronous dynamic random access memory will be described with reference to FIG. 3.
If, at the rise-time of the clock signal CLK, the row address strobe bar and the chip select bar are low level whilst the column address strobe bar and the write enable bar are high level, then those combinations of the signals means "active command", whereby the command decoder 81 is operated to make the internal command signal 71 in high level which indicates the input of the active command. Namely, the internal command signal 71 is made into the high level. After the internal command signal 71 was made into the high level, then a column address control signal 73 is made into the low level. Thereafter, if the internal command signal 71 is returned to the low level, then the column address control signal 73 remains low level. Consequently, the conventional row address control signal generator circuit is operated so that when the column address control signal 73 is made into the low level, the row address circuit is activated.
If, in rise-time of the clock signal CLK, the row address strobe bar, the write enable bar and the chip select bar are low level whilst the column address strobe bar is high level, then the command decoder 81 is operated to make the internal command signal 72 into the high level during one cycle so as to indicate the input of the pre-charge command. In the activated state of the row address control signal, the internal command signal 72 is made into high level, whereby the row address control signal 73 is made into high level. As a result, if the internal command signal 72 is made into low level, then the row address control signal 73 remains high level.
It is hereby assumed that the write command was inputted in a clock cycle which is prior to, by one cycle, the clock cycle during which the pre-charge command is inputted. By input of the write command, the column address control signal not illustrated is activated to execute the write operation by taking a predetermined time from the input of the command.
In FIG. 3, the externally inputted clock signal has a clock cycle time t78. It takes a time t77 to inactivate the row address control signal after the pre-charge command has been inputted. This time period t77 is independent from the clock cycle t78. If the write command is inputted in the cycle just prior to the cycle during which the pre-charge command is inputted, it takes a time period t79 to inactivate the row address control signal from the rise-edge of the clock signal externally inputted upon the input of the write command. The time period t79 is the sum of the time period t77 and the time period t78. Namely, the time period t79 is dependent upon the clock cycle t78.
It takes a predetermined time after the write command was inputted to execute the write operation before the row address control signal is inactivated so that a word line is placed into a non-selected state, whereby a write operation is first permitted. This means it required to ensure a sufficiently long time period t79 for entry into the write enable state.
Since the time period t77 is independent from the clock cycle t78, the write enable state depends upon the clock cycle t78.
There is, however, a possibility of the appearance of a problem during a time period after the write operation and before the pre-charge operation. This problem is concerned with the insufficient write of data into the memory cells.
This problem is likely to appear when a contact resistance of the memory cell is extremely high. This causes a defective bit, for which reason such defective memory cell should be detected by a wafer test and relived by a redundancy circuit to realize a high yield.
The test of the synchronous dynamic random access memory is conducted by use of a memory tester, predetermined signals are inputted into a CLK pin, a CKE pin, a CS bar pin, an RAS bar pin, a CAS bar pin and a WE bar pin as well as a plurality of address pins and a plurality of data pins, in addition a power pin and a ground pin.
If the wafer is tested, a probe card is used to connect individual pads connected to the external input pins to individual pins of the memory tester.
The synchronous dynamic random access memory shows high speed operations, for which reason in order to conduct a sufficient test for all functions thereof, it is required to use a memory tester operable in high frequency range and a accurate tester jig. This test is a costly procedure.
Some of advanced synchronous random access memories are operated at a high frequency of not less than 100 MHz. In this case, it is difficult to input high frequency signals thereto. Due to the capacitance of the probes and the contact resistance to the pads of the device, the pulse signals are rounded. For this reason, it is difficult to conduct the test by inputting the high frequency signals. Actually, the wafer test is conducted by inputting a relative low frequency signal even when the device has a high speed performance.
In prior art, there is a problem with difficulty to conduct a timing-test restricted by the clock cycle of the externally inputted clock signal by use of a relatively low frequency tester, for example, when the pre-charge command is inputted into the cycle following to the cycle in which the write command was inputted.
There is another problem with difficulty in conducting a wafer test by inputting a high frequency signal.
In the above circumstances, it had been required to develop a synchronous semiconductor memory device free from the above problems.